This invention relates to a semiconductor memory device and more particularly to a nonvolatile semiconductor memory device such as a NAND cell, NOR cell, DINOR cell or AND cell type EEPROM.
As one type of a semiconductor memory device, an EEPROM capable of electrically programming data is known. A NAND cell type EEPROM having NAND cell blocks each constructed by serially connecting a plurality of memory cells has received much attention since it is integrated with high density.
One memory cell in the NAND cell type EEPROM has an FET-MOS structure which has a floating gate (charge storing layer) and control gate stacked on a semiconductor substrate with an insulating film disposed therebetween. A plurality of memory cells are serially connected with the adjacent two of the memory cells commonly using the source/drain to construct a NAND cell and the NAND cell is dealt with as one unit and connected to a bit line. The NAND cells are arranged in a matrix form to construct a memory cell array. Generally, the memory cell array is integrated on a p-type semiconductor substrate or p-type well region.
The drains on one-end sides of the NAND cells arranged in the column direction of the memory cell array are commonly connected to a bit line via selection gate transistors and the sources thereof on the other sides are connected to a common source line via selection gate transistors. The control gates of the memory cells and the gate electrodes of the selection transistors are formed to continuously extend in the row direction of the memory cell array and used as control gate lines (word lines) and selection gate lines.
The operation of the NAND cell type EEPROM with the above construction is as follows. First, the data programming operation is sequentially effected for the memory cells starting from the memory cell which is formed in position farthest away from the bit line contact. A high voltage Vpp (=approx. 20V) is applied to the control gate of the selected memory cell, an intermediate voltage Vmc (=approx. 10V) is applied to the control gates and selection gates of memory cells lying on the bit line contact side with respect to the selected memory cell and a voltage of 0V or intermediate voltage Vmb (=approx. 8V) is applied to the bit line according to data. When 0V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, thereby causing electrons to be injected from the drain into the floating gate. As a result, the threshold voltage of the selected memory cell is shifted in a positive direction. This state is defined as xe2x80x9c1xe2x80x9d. On the other hand, if the intermediate voltage Vmb is applied to the bit line, injection of electrons does not occur and the threshold voltage is not changed and is kept negative. This state is defined as xe2x80x9c0xe2x80x9d.
The data erase operation is effected for all of the memory cells in the selected NAND cell block. That is, all of the control gates in the selected NAND cell block are set to 0V and a high voltage of approx. 20V is applied to the bit line, source line, p-type well region (or p-type semiconductor substrate), and all of the selection gates and control gates in the non-selected NAND cell blocks. As a result, electrons in the floating gates of all of the memory cells in the selected NAND cell block are discharged into the p-type well region (or p-type semiconductor substrate) to shift the threshold voltage in the negative direction.
Further, the data readout operation is effected by setting the control gate of a selected memory cell to 0V, setting the selection gates and control gates of the memory cells other than the selected memory cell to a power supply voltage Vcc and determining whether or not a current flows in the selected memory cell.
Next, the memory cell array, block arrangement and the construction of the NAND cell in the NAND cell type EEPROM are explained in detail.
FIG. 32 shows the block arrangement of the memory cell array in the conventional NAND cell type EEPROM described above. In FIG. 32, all of the blocks 1-0 to 1-N in the memory cell array 1 are formed of NAND cells (which are referred to as NAND-A cells) of the same construction. To each of the blocks 1-0 to 1-N, selection gate lines SG1, SG2 and control gate lines CG(1) to CG(8) are connected. According to a row address, the block and the row of the NAND cell are selected so that a voltage can be supplied to the selection gate lines SG1, SG2 and control gate lines CG(1) to CG(8) from a row decoder.
FIG. 33 shows an example of the detail construction of part of the memory cell array 1 shown in FIG. 32 and is an equivalent circuit diagram of the memory cell array having the NAND cells arranged in a matrix form. Each of the blocks 1-0 to 1-N in the memory cell array 1 shown in FIG. 32 corresponds to an area 1-L (L=0 to N) indicated by broken lines in FIG. 33. In this example, a NAND cell group commonly having the same word line and selection gate line is called a block and the area 1-L surrounded by the broken lines in FIG. 33 is defined as one block. The drain of a selection gate transistor S1 of each NAND cell is connected to a corresponding one of bit lines BL1, BL2, . . . , BLm and the source of a selection gate transistor S2 is connected to a common source line CS. Memory cells M1, M2, . . . , M8 are serially connected between the source of the selection gate transistor S1 and the drain of the selection gate transistor S2. The operation such as the readout/program operation is generally effected by selecting one block (which is called a selected block) from a plurality of blocks by use of the selection gate transistors S1, S2.
FIGS. 34A, 34B and FIGS. 35A, 35B show in detail one NAND cell extracted from the circuit shown in FIG. 33. FIGS. 34A, 34B are a pattern plan view and equivalent circuit diagram of a NAND cell portion and FIGS. 35A, 35B are cross sectional views respectively taken along the A-Axe2x80x2 line and B-Bxe2x80x2 line of the pattern shown in FIG. 34A. A memory cell array formed of a plurality of NAND cells is formed on a p-type silicon substrate (or p-type well region) 11 surrounded by an element isolation oxide film 12. In this example, eight memory cells M1, M2, . . . , M8 are serially connected in each NAND cell.
In each of the memory cells M1, M2, . . . , M8, a floating gate 14 (141, 142, . . . , 148) is formed above the substrate 11 with a gate insulating film 13 formed therebetween and a control gate 16 (161, 162, . . . , 168) is formed above the corresponding floating gate with a gate insulating film 15 formed therebetween. Further, n-type diffusion layers 19 (191, 192, . . . , 198) used as the sources and drains of the memory cells are connected with the sources/drains of the adjacent memory cells commonly used so as to construct the series-connected memory cells M1, M2, . . . M8.
Selection gates 149, 169 and 1410, 1610 which are formed in the same step as the floating gates and control gates of the memory cells are formed on the drain side and source side of the NAND cell. The selection gates 149, 169 and 1410, 1610 are electrically connected to each other in an area (not shown) and respectively used as the gate electrodes of the selection gate transistors S1, S2. The upper surface of the substrate 11 on which the elements are formed is covered with a CVD oxide film (inter-level insulating film) 17 and bit lines are formed on the CVD oxide film 17. The bit line 18 is formed in contact with a diffusion layer 190 on the drain side of one end of the NAND cell. The control gates 14 of the NAND cells arranged in the row direction are respectively commonly arranged as the control gate lines CG(1), CG(2), . . . , CG(8). The control gate lines are used as word lines. The selection gates 149, 169 and 1410, 1610 are also arranged continuously in the row direction as the selection gate lines SG1, SG2. A wiring layer 22 for the source line is disposed between the bit line 18 and a wiring layer exclusively used for the control gate line/selection gate and is formed in contact with a diffusion layer 1910 on the source side of the NAND cell (on the end opposite to the bit line contact portion).
Thus, conventionally, the memory cells of the same dimensions and same construction are formed in each block of the memory cell array.
In the memory cell array shown in FIG. 32, since the blocks are regularly arranged, the control gate lines CG(1) to CG(8) and selection gate lines SG1, SG2 are arranged at substantially regular intervals in the entire memory cell array, and therefore, the processing precision for the word lines or the like becomes relatively high in the blocks (corresponding to the blocks 1-1 to 1-(N-1) shown in FIG. 32) lying inside the memory cell array 1. However, since the wiring pattern becomes irregular in the blocks (corresponding to the blocks 1-0, 1-N shown in FIG. 32) lying on the end portion of the memory cell array, particularly, in a portion near the outer periphery (near the selection gate line SG2 in FIG. 33) of the memory cell array 1, the etching condition cannot be made constant and the processing precision is lowered.
Generally, the blocks in the end portion of the memory cell array are dealt with as non-use blocks by taking it into consideration that the processing precision is lowered, but even in this case, it is not a satisfactory measure, and the selection gate line SG2 in the block 1-0, 1-N of FIG. 32 is cut off or it short-circuits to a source line contact portion by an increase in the wiring width of the selection gate line SG2, thus causing a problem. Generally, the selection gate lines SG1, SG2 are wirings whose potentials are determined according to the selection/non-selection of the block and the influence given by the non-selected block at the time of program/readout operation, for example, is eliminated by setting the bit lines, source line and NAND cell into the non-selected state when the block is not selected. However, if the line is cut off, it is difficult to set the non-conductive state. In this case, there occurs a problem that a leak current flows from the bit line, the load capacitance of the bit line and source line is increased, or a short circuit between the bit line and the source line occurs, and the operation margin is reduced and the operation may become defective. Further, when the selection gate line SG2 is short-circuited to the source line contact portion, the source line voltage and the voltage of the selection gate line SG2 may vary and a defect occurs.
A problem of a lowering in the processing precision due to disturbance of the regular arrangement of the wiring pattern may occur not only in the entire memory cell array but also in one NAND cell if higher precision is required. Next, a lowering in the processing precision in a case where special attention is given to one NAND cell is explained in detail with reference to FIGS. 36A, 36B, 37A, 37B. FIGS. 36A, 36B are a pattern plan view and equivalent circuit diagram showing one NAND cell portion of the memory cell array, and FIGS. 37A, 37B are cross sectional views taken along the A-Axe2x80x2 line and the B-Bxe2x80x2 line of FIG. 36A. In FIGS. 36A, 36B, 37A, 37B, portions which are the same as those of FIGS. 34A, 34B, 35A, 35B are denoted by the same reference numerals and the detail explanation therefor is omitted.
In this example, the line widths of the selection gate lines SG1, SG2 in FIGS. 36A, 36B, 37A, 37B are denoted by Wsg1, wsg2, the line widths of the control gate lines CG(1), CG(2), . . . , CG(8) are denoted by Wcg1, Wcg2, . . . , Wcg8, spaces between the control gate lines are denoted by Scg12, Scg23, . . . , Scg78, and spaces between the control gate lines and the selection gate lines are denoted by Ssg1, Ssg2. The NAND cell shown in FIGS. 36A, 36B, 37A, 37B is different from the NAND cell shown in FIGS. 34A, 34B, 35A, 35B in that the wiring layer 22 for the source line is not provided.
In the above NAND cell, conventionally, the designed values of all of the control gate line widths in the NAND cell are the same. That is, in FIGS. 36A, 37A, Wcg1=Wcg2= . . . ,=Wcg8. Further, the spaces between the control gate lines are set to the same value, that is, Scg12=Scg23 = . . . , Scg78. On the other hand, the selection gate line width is designed to be slightly larger than the control gate line width in order to enhance the cut-off characteristic of the selection gate transistors S1, S2 (reduce the leak current at the time of SG1=SG2=0V).
Further, the wiring layer 14 for the selection gate lines SG1, SG2 is formed continuous (the wiring layer 14 is made continuous in a portion between the selection gate transistors which are adjacent in a direction along the selection gate line) and the wiring layer 14 for each control gate line CG is divided between the memory cells (refer to the hatched portion in FIG. 36A). Therefore, in order to lower the damage to the wiring layer 14 of the selection gate line portion at the time of processing of the wiring layer 14 of the control gate line portion, the spaces Ssg1, Ssg2 mat be made larger than Scg12 to Scg78 in some cases.
Thus, in the conventional NAND cell, the line widths and spaces of and between the control gate lines CG(1) to CG(8) are regularly set (with the same dimensions), but the regularity of the wiring arrangement is not attained in an area (corresponding to an area above the control gate line CG(1) or below the control gate line CG(8) of FIG. 36A) other than the arrangement area of the control gate lines. Therefore, there occurs a problem that the processing for the control gate lines CG(1) and CG(8) on both end portions of the CG line arrangement portion becomes unstable in comparison with the control gate lines CG(2) to CG(7) which are arranged with the regularity with respect to the adjacent wirings, that is, the processing precision is lowered. If the processing precision is lowered, the line width of the control gate line adjacent to the selection gate line or the channel length of a corresponding memory cell varies depending on a variation in the processing precision.
The most serious problem occurring when the processing precision is lowered may occur in a case where the line widths of the control gate lines CG(1) and CG(8) on both end portions become smaller than the designed value. The problem is explained with reference FIGS. 38A, 38B. If the line width of the control gate line CG(1) is set to the designed value, as shown in FIG. 38A, no current (leak current IL) flows in a memory cell having xe2x80x9c1xe2x80x9d data (in a state in which negative charges are injected into the floating gate) when the gate voltage is 0V since the cut-off characteristic of the memory cell is good. If the line width of the control gate line CG(1) is made smaller than the designed value, a state in which a current IL always flows in the memory cell M1 is obtained and xe2x80x9c0xe2x80x9d data is always read out irrespective of data programmed into the memory cell, that is, the amount of charges in the floating gate 141 since the channel length of the memory cell M1 becomes shorter and the cut-off characteristic of the memory cell is lowered (a leak current (refer to FIG. 38B) in a state in which it is originally turned OFF increases). Therefore, there occurs a problem that correct data cannot be programmed or read out. Like the case of the control gate line CG(1), the same problem occurs when the line width of the control gate line CG(8) is made smaller than the designed value. If all of the eight control gate lines are made wide in order to solve the above problem, a new problem that the memory size becomes larger occurs.
In the above NAND cell, conventionally, wiring structures shown in FIGS. 39A, 39B are used for connecting the selection gate line and the control gate line which extend from the inside portion of the memory cell array to the row decoder. Generally, when a contact for connection between different wiring layers is made, the wiring layer which is to be formed in contact with the other wiring layer is charged in the etching step due to RIE or the like to increase the absolute value of the potential of the wiring in some cases. At this time, since the wiring which is not connected to a pn junction has no current path in which a voltage drop occurs, a high potential is maintained. In this case, the control gate line corresponding to the control gate of the memory cell causes a problem.
Generally, in a memory cell such as a NAND type EEPROM, conventionally, the control gate line is not connected to the pn junction and a high potential is applied thereto in the manufacturing process. At the time of data programming or erasing, a potential as high as approx. 20V is applied between the control gate line and the p-type well region. Further, it is required to inject/discharge electrons into or from the floating gate by 100,000 times or more by use of a tunnel current. Thus, an extremely intense electric field is applied to an insulating film (corresponding to an oxide film between the wiring layer 16i (i=1 to 8) and the wiring layer 14i (i=1 to 8) and an oxide film between the wiring layer 14i (i=1 to 8) and the p-type well region) between the control gate line and the p-type well region. In addition, since data is determined by charges stored in the floating gate, the charge storing characteristic of the floating gate becomes extremely important and discharging of charges from the floating gate due to the leak current cannot be permitted. Therefore, the reliability of the insulating film between the control gate line and the p-type well region is significantly important.
However, conventionally, the wiring is made by use of two types of wiring layers 22, 18 which are formed above the control gate line when the control gate line and selection gate line are connected to a transistor QN in the row decoder from the memory cell array. Therefore, the step of making a contact with the wiring layer 16i used as the control gate line is effected twice in the manufacturing process (corresponding to (xcex1) and (xcex2) in FIG. 39A). In this case, the control gate line is charged at the time of contact processing of (xcex1), and since the wiring layer 16i and the wiring layer 22 are already connected together via the contact (xcex1), the control gate line is also charged at the time of contact processing of (xcex2). Therefore, the period in which the high voltage is kept applied to the control gate line becomes long and stress applied to the control gate line becomes large, thereby degrading the film quality of the oxide film. As a result, the reliability of data stored in the memory cell is lowered and the possibility of data destruction becomes stronger.
In the case of the selection gate line, since the voltage applied thereto is approx. 10 at maximum and it has no floating gate (the wiring layer 14j (j=9, 10) is continuously arranged and a voltage is directly applied thereto inside or outside the memory cell array), normally, the reliability thereof is not lowered even if stress is somewhat applied thereto.
Thus, in the conventional semiconductor memory device such as the NAND cell type EEPROM, the processing precision for the block on the end portion of the memory cell array is lowered and there occurs a problem that the operation margin is lowered and the operation becomes defective.
Further, in the conventional semiconductor memory device such as the NAND cell type EEPROM, the processing precision for the control gate line adjacent to the selection gate line is lower than that for the other control gate line, and when the line width becomes smaller than the designed value, a problem that correct data cannot be programmed or read out occurs. Further, if the line widths of all of the control gate lines are uniformly made larger in order to solve this problem, a new problem that the memory cell size is increased occurs.
In addition, in the conventional semiconductor memory device such as the NAND cell type EEPROM, since stress applied to the control gate line in the manufacturing process is large, the reliability of an insulating film around the floating gate of the memory cell is lowered and the possibility of data destruction becomes stronger.
This invention has been made in order to solve the above problems and an object of this invention is to provide a semiconductor memory device capable of preventing occurrence of a defect caused by a lowering in the processing precision for an end area of a memory cell array and realizing a chip in which the reliability of the operation is high and the manufacturing yield is high without substantially increasing the chip size.
Further, another object of this invention is to provide a semiconductor memory device capable of preventing occurrence of a word line with an extremely small line width due to a lowering in the processing precision caused by loss or disturbance of the regular (regular-interval) arrangement of wirings around the word line and realizing a chip in which the reliability of data programming/readout is high without significantly increasing the chip size.
Still another object of this invention is to provide a semiconductor memory device capable of lowering stress applied to a memory cell in the manufacturing process, reducing the pattern area of a row decoder and realizing an inexpensive chip in which the reliability of the operation is high and the manufacturing yield is high.
According to the present invention, there is provided a semiconductor memory device comprising: a memory cell array having: first blocks including first memory cell units each having a plurality of at least one memory cell; and second blocks including second memory cell units each having at least one memory cell connected; wherein the first blocks are arranged on both end portions of the memory cell array, the second blocks are arranged in the other portion, and the structure of the first memory cell units on the end portions of the memory cell array is different from that of the second memory cell unit.
According to the present invention, there is still provided a semiconductor memory device comprising: a memory cell array having memory cells or memory cell units formed by connecting at least one memory cell, the memory cells or memory cell units being arranged in an array form; wherein selection gate lines are formed by use of a mask having a data pattern in which the width of at least one of a word line and a selection gate line arranged on the end portion of the memory cell array is set larger than that of at least one of a word line and selection gate line arranged on the other portion of the memory cell array.
According to the present invention, there is further provided a semiconductor memory device comprising: a memory cell array having memory cells or memory cell units formed by connecting at least one memory cell, the memory cells or memory cell units being arranged in an array form; wherein at least one of a word line and a selection gate line arranged on the end portion of the memory cell array is formed with a larger width than at least one of a word line and selection gate line arranged the other portion of the memory cell array.
According to the present invention, there is still further provided a semiconductor memory device comprising: a memory cell array having memory cells or memory cell units formed by connecting a plurality of memory cells, the memory cells or memory cell units being arranged in an array form; a word line unit having a plurality of word lines each connected to corresponding ones of the memory cells; and selection gate lines each being connected to corresponding memory cells or memory cell units, wherein the word lines are formed by use of a mask having a data pattern in which the line widths of those of the word lines which are arranged on both end portions of the word line unit is set larger than those of the word lines adjacent thereto.
According to the present invention, there is further provided a semiconductor memory device comprising: a memory cell array comprising memory cell units arranged in an array form, the memory cell units each comprising at least one memory cell and at least one selection transistor; at least one selection gate line formed by continuously extending the gate of the at least one selection transistor; and control gate lines formed by continuously extending the gates of the memory cells; a row decoder for selecting the at least one selection gate line and the control gate lines to control the potentials thereof, the row decoder comprising transistors; first wirings for connecting the control gate lines to corresponding transistors in the row decoder, respectively; and at least one second wiring each for connecting corresponding one of the at least one selection gate line to a corresponding one of the transistors in the row decoder, wherein the first wirings are different in structure from the at least one second wiring.
According to the present invention, there is further provided a semiconductor memory device comprising: a memory cell array having memory cell units arranged in an array form, the memory cell units each being formed of at least one memory cell connected, and each having at least one selection transistor; selection gate lines formed by continuously extending gates of the selection transistors of the memory cell units; control gate lines formed by continuously extending gates of the memory cells of the memory cell units; and a row decoder for selecting the selection gate lines and control gate lines of the memory cell array to control the potentials thereof, the row decoder comprising transistors; wherein the selection gate line is connected to a corresponding transistor in the row decoder from the memory cell array by use of a first wiring layer which lies above all of the wiring layers used for connecting the control gate lines to corresponding transistors in the row decoder from the memory cell array.
According to the construction of this invention, occurrence of a defect caused by a lowering in the processing precision in the end portion of the memory cell array can be prevented by making a block in the end portion of the memory cell array different from the other block in construction. Further, since only the block in the end portion of the memory cell array is made different from the other blocks in construction, a chip having high manufacturing yield and high operation reliability can be attained without substantially increasing the chip size.
In order to make the construction of the first memory cell unit on the end side of the memory cell array different from the second memory cell unit, the first wiring may be formed by use of mask having a data pattern in which the first wiring is wider than a corresponding second wiring in the second memory cell unit.
Alternatively, the first wiring may be made wider than a corresponding second wiring in the second memory cell unit.
As the first wiring, a selection gate line may be used.
Further, in order to make the construction of the first memory cell unit on the end side of the memory cell array different from the second memory cell unit, for example, a space between the contact in the first memory unit and an adjacent wiring may be made larger than a space between the contact in the second memory unit and an adjacent wiring.
The construction of the first memory cell unit on the end side of the memory cell array may be made different from the second memory cell unit by providing a contact in the second memory cell unit and omitting a contact in a corresponding portion in the first memory cell unit. In this case, the operation reliability and manufacturing yield can be significantly enhanced.
More specifically, as the above contact, a contact formed on a node on the source side of the memory cell unit may be used.
Further, the first block may be used as a dummy block or redundancy block.
Further, according to the construction of this invention, in order to solve a problem caused by a lowering in the processing precision due to disturbance of the regular (regular-interval) arrangement of the wirings or the like, the designed value of the word line width is selectively changed. More specifically, by setting the designed value of the line width of the control gate line adjacent to the selection gate line larger than the line width of the other control gate line, a degradation in the cut-off characteristic of the memory cell can be prevented even if the line width of the control gate line adjacent to the selection gate line becomes smaller than the designed value. Further, since those of the control gate lines in the NAND cell whose line widths must be increased are only two control gate lines adjacent to the selection gate lines, an increase amount in the memory cells is small. Therefore, a chip having high reliability in the data programming/readout operation can be attained without significantly increasing the chip size.
In the data pattern of the mask, the line widths of the word lines arranged on both ends of the word line group may be made larger than the line widths of the adjacent word lines.
Selection gate lines may be arranged adjacent to the word lines whose line widths are set larger in the data pattern of the mask.
A nonvolatile memory cell can be used as a memory cell and the control gate line formed above the floating gate can be used as the word line.
Further, according to the construction of this invention, since the number of times of operations for making a contact with the control gate line can be suppressed to one, stress applied to the control gate line in the manufacturing process can be reduced and the reliability of an insulating film around the floating gate can be enhanced. As a result, a chip having high operation reliability can be attained without increasing the chip size.
As a wiring layer used for connection of the control gate line extending from the end portion of the memory cell array to the transistor in the row decoder, a wiring layer formed below the second wiring layer can be used.
In the wiring length of a wiring layer used for connection of the control gate line extending from the end portion of the memory cell array to the transistor in the row decoder, it is preferable to occupy at least the half portion thereof by a wiring of the second wiring layer and, in the wiring length of a wiring layer used for connection of the selection gate line extending from the memory cell array to the transistor in the row decoder, it is preferable to occupy at least the half portion thereof by a wiring of the first wiring layer.
Further, according to the construction of this invention, since the number of times of operations for making a contact with the control gate line can be suppressed to one and a current path formed of a pn junction for preventing the control gate from being charged to a high voltage is formed in the contact forming step, stress applied to the control gate line in the manufacturing process can be reduced and the reliability of an insulating film around the floating gate can be enhanced. As a result, a chip having high operation reliability can be attained without increasing the chip size.
The selection gate line may be connected from the memory cell array to a transistor in the row decoder by use of a second wiring having no connection with the pn junction other than the source/drain of the transistor in the row decoder.
The uppermost wiring layer among the wiring layers constructing the first wiring can be formed of the same wiring layer as the uppermost wiring layer among the wiring layers constructing the second wiring, and in this case, both of the wiring layers can be formed in the same manufacturing step.
The uppermost wiring layer among the wiring layers constructing the first wiring can be formed of a wiring layer which is formed below the uppermost wiring layer among the wiring layers constructing the second wiring, and in this case, the first and second wirings can be formed in a superposed configuration and the pattern area can be reduced.
The first wiring can be connected to both of the p-type and n-type diffusion layers, and in this case, since a current path for discharging charges in either case wherein positive or negative charges are charged is formed when the wiring tends to be charged at the time of formation of a contact between the wirings in the manufacturing process, stress applied to the memory cell caused by charges in the etching process can be significantly reduced. Further, application stress can be more effectively reduced by using the forward current in the pn junction which is larger than the reverse current.
The first wiring can be formed of a wiring layer which is formed below a wiring layer capable of being directly connected to the wiring layer forming the control gate line in the memory cell array without using an additional intervening wiring layer.
The second wiring can be formed to include a wiring layer which is formed above a wiring layer capable of being directly connected to the wiring layer forming the control gate line in the memory cell array without using an additional intervening wiring layer.
For example, a NAND cell type EEPROM may be adequately used as the memory cell unit in this invention.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.